The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure within any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also increased the importance of, and attention to, semiconductor material properties and behaviors.
The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Every device must be smaller without damaging the operating characteristics of the integrated circuit devices. High packing density, low heat generation, and low power consumption, with good reliability and long operation life must be maintained without any functional device degradation. Increased packing density of integrated circuits is usually accompanied by smaller feature size.
As integrated circuits become denser, the widths of interconnect layers that connect transistors and other semiconductor devices of the integrated circuit are reduced. As the widths of interconnect layers and semiconductor devices decrease, their resistance increases. As a result, semiconductor manufacturers seek to create smaller and faster devices by using, for example, a copper interconnect instead of a traditional aluminum interconnect. Unfortunately, copper is very difficult to etch in most semiconductor process flows. Therefore, damascene processes have been proposed and implemented to form copper interconnects.
Damascene methods usually involve forming a trench and/or an opening in a dielectric layer that lies beneath and on either side of the copper-containing structures. Once the trenches or openings are formed, a blanket layer of the copper-containing material is formed over the entire device. Electrochemical deposition (ECD) is typically the only practical method to form a blanket layer of copper. The thickness of such a layer must be at least as thick as the deepest trench or opening. After the trenches or openings are filled with the copper-containing material, the copper-containing material over them is removed, e.g., by chemical-mechanical planarization or polishing (CMP), so as to leave the copper containing material in the trenches and openings but not over the dielectric or over the uppermost portion of the trench or opening.
During CMP, copper and the adjacent dielectric are removed from the wafer at different rates. Typically, a copper-selective chemical slurry is applied, after which a first round of polishing occurs. Then, a dielectric-selective slurry is applied, followed by more polishing. This process creates certain surface anomalies, and a varying post-CMP topography. A number of factors, including pattern geometry (e.g., copper line density), affect the removal rates and add to the surface anomalies. One common surface anomaly that occurs with copper CMP is dishing. Dishing occurs when the copper recedes below or protrudes above the level of the adjacent dielectric. Theoretically, the goal of the CMP process is to achieve a flat post-CMP topography, as excessive dishing can negatively impact process yields. In practice, however, some processes may achieve more optimal yields with a slight, or even moderate, amount of dishing. Regardless of whether a flat or slightly dished topology is desired, the ability to monitor and actively control the amount of dishing is critical to achieving optimal process yields.
A number of conventional methods exist by which post-CMP topography is managed or regulated. Typically, such methods include some process for predicting or measuring polish rate, and some mechanism that uses that polish rate to calculate a required total polish time.
Unfortunately, a number of such conventional methods either fail to account for, or insufficiently account for, a number of complex multi-variable interactions that can significantly impact a CMP process—such as pad conditioning, CMP environmental factors (e.g., temperature), slurry composition or material degradation. In order for a conventional system to adequately account for such variables, an accurate complex multi-variable model would be required. Developing such an accurate model, if possible at all, would be a very labor-intensive task. Furthermore, such a model would require extensive data and behavioral maintenance. Thus, frequently, conventional CMP processes rely on simple, best-guess models or historical data extrapolations.
In the absence of a highly accurate polishing rate model, however, a number of processes may fail to polish a device with acceptable accuracy—particularly where stringent process specifications exist (e.g., shallow trench isolation devices). Even nominal variations between predicted polish rates and actual polish rates can yield significant under or over polish results. Where such results are recognized, process overhead may be increased, as under-polished wafers must undergo some remediation, or process yields may suffer as over-polished wafers are scrapped. Where such results are not recognized, device reliability and yields may suffer.
As a result, there is a need for a versatile system for controlling the post-CMP topology of a semiconductor wafer—a system that provides direct and dynamic control of CMP processing in an easy, efficient and cost-effective manner.